Dr. Maneatis has published three papers in the IEEE Journal of Solid-State Circuits (JSSC), all of which were presented at the International Solid-State Circuits Conference (ISSCC). He served on the ISSCC's Digital Program Committee for eight years and served as active associate editor of the JSSC for three years. Dr. Maneatis and his staff have also published a number of papers and articles in industry magazines and at industry trade shows.

Why Synthesizable-digital PLLs Are No Substitute for Hardened Mixed-signal PLLs,
    Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis

The Secret to Building IP,
    2016 REUSE Conference paper based on presentation by John Maneatis

Phase-Locked Loops Demystified,
    Chip Estimate's IP Connections Newsletter article by John Maneatis and Eskinder Hailu

Selecting PLLs for ASIC Applications Requires Tradeoffs,
    2004 FSA Semiconductor IP Workshop paper by John Maneatis

Self-Biased High-Bandwidth Low-Jitter 1-to-4096 Multiplier Clock Generator PLL,
    IEEE Journal of Solid-State Circuits paper by John Maneatis
    (2003 ISSCC 24.2 presentation slides for this paper)

Hidden Complexities of PLLs Are Revealed,
    Integrated System Design article by John Maneatis

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,
    IEEE Journal of Solid-State Circuits paper by John Maneatis
    (1996 ISSCC 8.1 presentation slides for this paper)

Precise Delay Generation Using Coupled Oscillators,
    IEEE Journal of Solid-State Circuits paper by John Maneatis
    (1993 ISSCC 7.5 presentation slides for this paper)