True Circuits, Inc.

True Circuits provides five general categories of low-jitter PLL hard macros: Clock Generator PLLs, Deskew PLLs, Spread Spectrum PLLs, Low Bandwidth PLLs, and High Resolution PLLs. We also offer low-jitter DDR DLL hard macros. These hard macros have excellent jitter performance while operating in the hostile mixed-signal noise environment present in today's ICs. They span nearly all performance points and features typically requested by ASIC, FPGA and SoC designers. Our PLLs support wide frequency and multiplication factor ranges and include special circuitry called LockNow!™ technology that allows for very fast locking with minimal frequency overshoot. Our DLLs have excellent linearity, very high resolution and are ideal for high-speed DDR interface applications. These PLL and DLL hard macros are available in TSMC, UMC, Chartered and Common Platform logic processes from 0.25um to 40nm.

PLLs have historically faced a tradeoff between typically undesirable options. True Circuits' LockNow! technology obliterates this tradeoff. LockNow! PLLs achieve lock in essentially constant time at a particular output frequency independent of feedback divider and bandwidth settings, regardless of the loop bandwidth for a given output frequency, and add no additional frequency overshoot. Unlike competing designs, LockNow! PLLs have no special modes that require external control and no lurking failure mechanisms found only on the production line. Circuit designers employing LockNow! PLLs can typically expect two or more orders of magnitude improvement in lock times with the same level of input period jitter rejection as before.

True Circuits' continuous product improvements are driven by lab experience, customer requirements and our unique understanding of the PLL design problem. LockNow! technology is just one of the many improvements that we have standardized into our entire family of PLL designs and rolled out to our customers over the last few years. In this case, LockNow! technology was developed for customers with fast start-up time requirements, usually stemming from low-power designs which power down the PLL when not active. However, as there is no tradeoff with LockNow! technology, all our PLL customers benefit from this significant improvement.




The High Resolution PLL is designed as a high frequency resolution clock multiplier with over 16 bits of control while operating with a high loop bandwidth to produce very low long-term jitter. It delivers optimal jitter performance over all multiplication settings. It can also be configured to provide precise spread-spectrum behavior for system clock EMI reduction. This PLL is ideal for system clock generation, built-in frequency margin testing, SERDES and video clock applications.




The Low Bandwidth PLL is designed to multiply an input clock by a fixed-point number between 1 and 16 with a low adjustable loop bandwidth. It does not provide any deskew functionality. The low loop bandwidth provides filtering of reference input jitter. It contains a 1-16 divider at the reference clock input, a 1-16 integer divider and a 1-256 fractional divider in the internal feedback path, and a 1-8 divider at the output. The loop bandwidth is inversely controllable with a relative range of 1-256. The outputs are 50% duty cycle for all output divider values.




The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable for PC and consumer electronics applications. It does not provide any deskew functionality. It contains a 1-64 divider at the reference clock input, a 1-256 integer divider and a 1-256 fractional divider in the internal feedback path, and a 1-8 divider at the output. It can generate adjustable frequency spreading amounts (0.6% typical) and rates in the range (30KHz typical). The outputs are 50% duty cycle for all output divider values.




The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the clock reference by an integer between 1 and 4. It provides three 50% duty cycle skew aligned outputs that are divided down from the internal VCO frequency by 1, 2, and 4.




The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It contains a 1-32 divider at the reference clock input, a 1-4096 divider in the internal feedback path, and a 1-8 divider at the output. The outputs are 50% duty cycle for all output divider values. It also programmably provides 2, 4, or 8 output phases that precisely subdivide the output clock period. Selecting 4 or 8 phases divides the output by an additional 2 or 4, respectively.




The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock cycle. It uses a phase-locked analog delay line which rejects temperature and supply voltage variations, and has high supply noise rejection for very low jitter operation. TCI can configure this block to have almost any number of slaves (which delay the arbitrary signals) with a single master section (which establishes the time base) to minimize area and power. The slave delays can be independently set to precise values or dynamically adjusted after determining the boundaries of a data eye. The DDR DLL has excellent linearity and very high resolution. The analog delay-line architecture used in our DLL design sharply contrasts with those used in digital DLL approaches. The analog control loop allows our DLL to continuously and smoothly compensate its delays to changing voltage and temperature conditions, without any quantization jitter or output glitches. However, digital delay-line control loops, which typically multiplex between inverter outputs along a string of inverters, must select between quantized delay values. Such approaches can lead to imprecise delays and either output glitches from updates or timing drifts from voltage and temperature variations in the absence of updates. The analog delay line used in our DLL design is internally isolated from supply noise for very low output jitter, while digital delay lines tend to be very supply noise sensitive as they convert it percent-for-percent into output jitter. Our analog delay line also provides pulse width compensation to minimize pulse width distortion, unlike digital delay lines. Finally, our DLL design provides very high digital adjustment resolution (typically 7 bits), where the steps are precise fractions of the clock period, unlike digital DLL designs where the adjustment steps are very large and not well calibrated.