The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individually, correcting skew within byte lanes. This state-of-the-art tuning acts independently on each pin, data phase and chip select value. Read gate and data eye timing are also continuously adjusted. Automatic training is included for multi-cycle write leveling and read gate timing, read/write data eye timing, and PHY Vref and DRAM Vref settings.

Remarkable physical flexibility allows the PHY to adapt to each customer's die floorplan and package constraints, yet is delivered and verified as a single unit for easy timing closure with no assembly required.

The PHY is DFI 5.1 compliant, and when combined with an appropriate DDR memory controller, a complete and fully-automatic DDR system is realized. The PHY is silicon proven and immediately available in the TSMC 28nm HPC/HPC+ process, with additional foundry processes to follow.

DDR 4/3 PHY Product Brief


* Supports LPDDR5, DDR4, LPDDR4, DDR3, LPDDR3

* DFI 5.1 compliant

* Supports x4, x8 and x16 DRAMs

* Up to 72 bits wide

* Up to 4 ranks

* Includes PLL, with frequency multiplication from low frequency reference

* Per pin architecture automatically corrects skew, increases data eye and eliminates most parallel interface problems

* Fully automatic training is managed by a light weight special purpose processor

* Continuous adjustment of read gate and data eye timing

* Automatic Training includes:
-- Multi-cycle write leveling
-- Multi-cycle read gate training
-- Per-pin read data eye training (including PHY Vref)
-- Per-pin write data eye training (including DRAM Vref)

* Localized and optimized PHY-to-memory controller interface to ease timing closure

* Full speed read/write BIST with pseudo-random data, mux-scan ATPG and 1149.1 Boundary Scan

Tuning for Performance

The PHY has been designed from the ground up to provide extensive, automatic and continuous tuning. Each pin constantly adjusts separate read data eyes for even and odd data phases, taking jitter into account. Tuning is also done separately for each chip select value. Pervasive tuning is the key to performance.

Timing Closure

To accelerate timing closure of the DDR PHY to the memory controller, the interface from PHY to memory controller is synchronous and localized.

Automatic Training

DDR systems require a great deal of training to function properly. The TCI PHY performs all of the required training with no user interaction by utilizing a light weight special purpose processor. Low overhead, incremental training can be done at the user's discretion to achieve even higher data rates.

Automatic training includes multi-cycle write leveling and read gate training, and per pin read and write data eye training.

Tools

TCI uses many proprietary tools to achieve a level of quality, flexibility and automation unseen in mixed-signal design, and not currently available in this type of hard IP.

No Assembly Required

The PHY is fully tested and verified with state-of-the-art timing analysis. Through a careful, joint process, the I/O ring and package are co-designed prior to PHY delivery, so that the PHY can be fully described, verified and delivered as a whole. Tremendous flexibility is allowed and no assembly is required.

Lower Package and Board Costs

Simpler and cheaper (fewer layers) chip packages and boards can be designed with reduced requirements for matched trace lengths and more flexibility in the I/O ring/package co-development.

Measurement Resources for Characterization

The PHY contains many resources that can be set up to quickly characterize a new chip, a package or a customer's PCB board. Per pin measurements include: DQ switching jitter, read DQS jitter, read data eye, write data eye, Vref sensitivity and flight times. Pin and pattern weaknesses can be found quickly, without expensive lab equipment. Using an appropriate controller, the DDR interface can be fully characterized without CPU interaction.

Test

The PHY includes a full speed read/write BIST, which tests the complete read and write paths of every pin simultaneously with pseudo-random data. The PHY design kits include industry-standard boundary scan chains and all the appropriate views for DFT.

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