"Our connected media devices deliver class-leading performance at the lowest possible power consumption. True Circuits' clock generator PLLs have wide programmable frequency ranges, low jitter, small area and low power. This mix of performance and functionality enables us to offer our customers highly differentiated IP cores in advanced process technologies."

Mark Dunn
General Manager IMGworks
Imagination Technologies



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


22 Apr 14 TSMC NA Technology Symposium
San Jose, California

1 May 14 TSMC NA Technology Symposium
Austin, Texas

2-4 Jun 14 Design Automation Conference
San Francisco, California

30 Sep 14 TSMC OIP Ecosystem Forum
San Jose, California

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