"We chose TCI because of their expertise in PLLs and the proven nature of their PLL designs. By going with TCI in the future, we feel we can spend more time designing our embedded cores and less time doing test chip integration work."

Ken Reimer, Austin Design Center Manager, ARM

When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.