"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



The PLL licensing fees do not include royalties. They permit a specific TCI PLL design for a specific semiconductor process to be used in a single production chip design and its future versions that correct functionality. TCI PLLs can be used on additional chip designs for additional licensing fees.


1 May 18 TSMC NA Technology Symposium
Santa Clara, California

9 May 18 TSMC NA Technology Symposium
Austin, Texas

22 May 18 TSMC China Technology Symposium
Shanghai, China

25-27 Jun 18 Design Automation Conference
San Francisco, California

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