"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers."

Hans Bouwmeester
Director of IP
Open-Silicon



A TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. Spread-spectrum PLLs can also be used to generate the system clock to lower EMI emissions.


15 Mar 16 TSMC NA Technology Symposium
San Jose, California

24 Mar 16 TSMC NA Technology Symposium
Austin, Texas

6-8 Jun 16 Design Automation Conference
Austin, Texas

22 Sep 16 TSMC OIP Ecosystem Forum
San Jose, California

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