"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



Not usually. All our cell names are prefixed by "TCI_cellname_". As a result, our PLLs do not conflict with each other, and they usually don't conflict with our customers' cell names.


15 Mar 17 TSMC NA Technology Symposium
San Jose, California

22 Mar 17 TSMC NA Technology Symposium
Austin, Texas

19-21 Jun 17 Design Automation Conference
Austin, Texas

13 Sep 17 TSMC OIP Ecosystem Forum
San Jose, California

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