"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers."

Hans Bouwmeester
Director of IP
Open-Silicon



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


23 Jun 25 True Circuits Announces New and Improved Low-jitter Digital Ultra+ PLL that Offers Exceptional Performance, Features and Ease of Use

19 Jun 25 True Circuits Introduces the Low-jitter Digital Ultra+ PLL at the Design Automation Conference
Will also showcase other high-performance PLL, DLL and DDR PHY IP and powerful JSPICETM Design Environment (JDETM)

24 Jun 24 True Circuits Introduces the JSPICETM Design Environment (JDETM) at the Design Automation Conference

06 Jul 23 True Circuits Attends 60th Design Automation Conference and Celebrates 25 Years of Timing Excellence!

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