"We chose TCI because of their expertise in PLLs and the proven nature of their PLL designs. By going with TCI in the future, we feel we can spend more time designing our embedded cores and less time doing test chip integration work."

Ken Reimer
Austin Design Center Manager
ARM



The Verilog model is very close but not perfect.

  • In steady state, the Verilog model does not model any jitter that might be present in the real PLL.
  • During startup, the Verilog model will achieve lock much more quickly than the actual PLL....
  • ...


17 Jul 20 True Circuits Participates in First Virtual DAC! Showcases Silicon Proven PLLs, DLLs and DDR 4/3 PHYs

31 May 19 True Circuits Demonstrates Silicon Proven DDR 4/3 PHY at DAC

22 May 19 Response to DeepChip.com article on the demise of analog PLLs, by John Maneatis

20 Jun 18 True Circuits Attends Design Automation Conference

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