"Our network processors offer highly integrated voice and data capabilities by combining powerful digital signal processors, flexible packet-processing engines, and industry-standard streaming interfaces all on a single die. True Circuits has enabled these products to shine with highly differentiated PLL and DLL IP over three process generations (90nm, 65nm and 40nm). We can count on True Circuits to deliver first time working silicon and faster time to market."

Surinder Dhaliwal
Executive Director
VLSI Core Engineering
Mindspeed Technologies



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


22 Apr 14 TSMC NA Technology Symposium
San Jose, California

1 May 14 TSMC NA Technology Symposium
Austin, Texas

2-4 Jun 14 Design Automation Conference
San Francisco, California

30 Sep 14 TSMC OIP Ecosystem Forum
San Jose, California

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