"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



We provide all of the following for each of our PLLs:

  • Complete specifications
  • User guidelines
  • Behavioral simulation model
  • Complete layout (GDSII)
  • Layout vs. schematic netlist
  • ...


15 Mar 16 TSMC NA Technology Symposium
San Jose, California

24 Mar 16 TSMC NA Technology Symposium
Austin, Texas

6-8 Jun 16 Design Automation Conference
Austin, Texas

22 Sep 16 TSMC OIP Ecosystem Forum
San Jose, California

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