"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



The Verilog model is very close but not perfect.

  • In steady state, the Verilog model does not model any jitter that might be present in the real PLL.
  • During startup, the Verilog model will achieve lock much more quickly than the actual PLL....
  • ...


03 Jun 13 True Circuits Introduces Revolutionary New DDR 4/3 PHY at Design Automation Conference

28 Jan 13 See Our Ad in the Winter Issue of Chip Design Magazine

31 May 12 True Circuits Attends Design Automation Conference

30 May 11 True Circuits Attends Design Automation Conference

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