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Q:
How do I generate the clocks for a DDR memory interface?
A: The DDR interface is a source-synchronous interface that uses a
single bus to carry data both to and from DRAMs. The clock is sent
along with the data in the form of a data strobe signal (DQS) with
a frequency equal to half of the data bit rate. A TCI deskew PLL,
which provides phase-aligned divide by 1, 2, and 4 clock outputs,
can facilitate generating the system clock signals, data strobes,
and internal double frequency clocks used to clock the output data.
In addition to a PLL, DLLs are also needed to center data strobe
signals on the outgoing or incoming data valid windows. Spread-spectrum
PLLs can also be used to generate the system clock to lower EMI
emissions.
TCI has developed a line of DLLs and spread-spectrum PLLs for DDR and
non-DDR applications. TCI's DLLs are designed to generate precise strobe
signal delays that can be programmed from 0 to 360 degrees of the reference
period. They delay multiple periodic or aperiodic signals independent of
voltage and temperature and deliver optimal jitter performance over a wide
frequency range. TCI's spread-spectrum PLLs are designed to multiply an
input clock by an integer or fixed-point number with a frequency spreading
capability suitable for PC, networking and consumer electronics applications
that require spread-spectrum clock sources to satisfy FCC requirements for
RF emissions.
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Q:
What is included in a design kit?
A: We provide all of the following for each of our PLLs:
- Complete specifications
- User guidelines (including functional, integration, layout, testability,
packaging, and board-level guidelines)
- Behavioral simulation model (Verilog)
- Timing synthesis model (Synopsys .LIB)
- Layout abstract (LEF)
- Complete layout (GDSII)
- Layout vs. schematic (LVS) netlist (SPICE)
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Q:
Can the LVS SPICE netlist provided be used in a circuit-level
simulation?
A: No, for several reasons.
- PLL simulations are very tricky to run. It is fairly straightforward
to get results that show the PLL works either much better or much
worse than it will in a real application. Part of the value that
we offer is that we have the expertise to properly simulate these
PLLs and that we have done a thorough job at it.
- In order to establish adequate performance margin to ensure correct
operation under all circumstances, many thousands of simulations
must be run under carefully established operating conditions,
which requires keen insight into what can go wrong and how to excite
possible failures.
- We do not want customers relying on the simulated performance of
our PLLs outside the specified operating ranges or instead of the
specified performance numbers. The specified performance is carefully
margined based not only on our carefully obtained simulation results,
but also on our insight into PLL designs.
- There is no need to use the SPICE netlist to include in a circuit
simulation of your complete design. Because the PLL is ideally
acting as a stable clock source, any "system-level" simulations
should use a "PULSE" statement instead. Margining for the impact
of PLL jitter on setup time should be accomplished by reducing
the effective clock period by the specified jitter levels, along
with those from the clock tree.
- It is not in our business interest to release the proprietary
aspects of our PLL designs. Our design kits do not include any
internal schematics and our licensing agreement does not permit
reverse engineering of our PLL designs.
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Q:
How accurately does the Verilog model predict the behavior of the PLL?
A: The Verilog model is very close but not perfect.
- In steady state, the Verilog model does not model any jitter that
might be present in the real PLL.
- During startup, the Verilog model will achieve lock much more
quickly than the actual PLL to speed up Verilog simulations. The
PLL specifications list the correct time required to achieve
lock.
- The number of cycles required by the verilog model for relock,
after a clock source or runtime divider changes, is also less than
the actual PLL.
- After the PLL reset has been de-asserted, the PLL will proceed
towards a "locked" state. During this transition from a low reset
frequency to a higher operating frequency, the PLL output a few
cycles that are higher then the final target frequency. The PLL
specifications list the maximum overshoot level. The Verilog
model may exhibit somewhat different behavior during this "locking"
transient.
In general, the chip operation should not depend on the behavior
PLL output clock until the PLL is completely locked.
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Q:
How do I interpret TCI PLL jitter specifications?
A: The jitter specifications are established based on the worst-case
performance of the PLLs under worst-case operating conditions (i.e.
worst-case operating frequency, supply voltage, and temperature,
and 10% VDD low-frequency supply/substrate noise) with appropriate
margin for their intended applications. They are not indicative
of the actual measured performance of the PLL which is typically
much better. However, in our experience, budgeting for better
performance from any PLL in most ASIC applications is a mistake.
Cycle-to-cycle jitter is the time variation in adjacent clock
periods. Its specification is given as x% peak-to-peak, which means
that under the worst-case operating conditions with a worst case
of 10% VDD low-frequency supply/substrate noise, the clock period
may occasionally become as much as x/2% shorter or x/2% longer than
the nominal value. This x/2% variation in cycle time must be
included in timing budgets.
The cycle-to-cycle jitter for a divided output clock is the same
percentage of the divided clock period as that for an undivided
clock in the worst case of low-frequency supply/substrate noise.
However, the cycle-to-cycle jitter for any divided clock expressed
in units of time cannot exceed twice the long-term jitter by their
definitions.
Input-to-output jitter, or tracking jitter, is the time deviation
between the PLL output edges and the reference clock edges. This
jitter is only significant at a clock-domain boundary, where data
is sampled by or transmitted to a clock domain separate from that
produced by the PLL.
Long-term jitter is the time deviation between the PLL output edges
and those of an ideal clock source. If the reference signal is
perfectly periodic such that it has no jitter, long-term jitter and
tracking jitter for the output signal are equivalent.
Cycle-to-cycle jitter plus long-term jitter or input-to-output
jitter is not a useful quantity. The long-term jitter number
fundamentally must be greater than the cycle-to-cycle jitter number
because in the best-case scenario it is made of the same components.
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Q:
Does the GDSII need to be in its own Cadence library?
A: Not usually. All our cell names are prefixed by "TCI_cellname_". As
a result, our PLLs do not conflict with each other, and they usually
don't conflict with our customers' cell names.
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Q:
We are finding LVS mismatches. Why?
A: If you are using the LVS deck supplied by the foundry, you should
not find any mismatches between our supplied layout and our supplied
LVS netlist. If use your own non-standard LVS deck, then you might
have matching problems. If you have LVS problems, please contact
TCI Support at (650) 949-3400 or support@truecircuits.com.
Q: I'm using a TCI PLL. How does the PLL affect my timing budgets?
A: The PLL specifications, along with those from the clock distribution
network and the clocked elements, play a key part in chip timing
budgets. When calculating the timing budgets, one may need to
consider the worst-case static phase offset, duty cycle error,
cycle-to-cycle jitter, and possibly tracking jitter from the PLL,
the worst-case skew and jitter from the clock distribution, and the
worst-case setup, hold, and clock-to-output times for the clocked
elements.
Cycle-to-cycle jitter is significant for setup-time or cycle based
path budgets but not for hold-time or race path budgets. Clock
distribution jitter is significant for setup-time budgets but less
for hold-time budgets, depending on the clock distribution structure.
Clock distribution skew is important for both setup-time and hold-time
budgets. Static phase offset along with tracking jitter is significant
for the setup and hold-time budgets of latches or registers receiving
data at the chip interface. Finally, duty cycle error must be
considered for latch-based designs where the timing of both clock
edges is significant.
A on-chip setup-time budget, which subtracts from the nominal clock
period to form the worst-case clock period, would typically be
composed of the following worst-case components:
- 1/2 peak-to-peak PLL cycle-to-cycle jitter
- 1/2 peak-to-peak jitter through clock distribution network
- skew from clock distribution network
- skew between different PLL outputs (only if multiple used)
- PLL duty cycle error (only for latch-based designs which use
both clock edges)
An on-chip hold-time budget would typically be composed of the
following worst-case components:
- 1/2 peak-to-peak jitter between clock distribution network
end points
- skew from clock distribution network
- appropriate margin for flip-flop hold-time characteristics
An off-chip setup-time budget, which is used to form the worst-case
clock period at the chip interface, would typically be composed of
the following worst-case components:
- 1/2 peak-to-peak PLL input-to-output jitter
- PLL static phase offset
- 1/2 peak-to-peak jitter through on-chip and off-chip clock
distribution network
- skew from on-chip and off-chip clock distribution network
- PLL duty cycle error (only for latch-based designs which use
both clock edges)
An off-chip hold-time budget, would typically be composed of the
following worst-case components:
- 1/2 peak-to-peak PLL input-to-output jitter
- PLL static phase offset
- 1/2 peak-to-peak jitter through on-chip and off-chip clock
distribution network
- skew from on-chip and off-chip clock distribution network
- PLL duty cycle error (only for latch-based designs which use
both clock edges)
- appropriate margin for flip-flop hold-time characteristics
The peak-to-peak amount of jitter through a well designed clock
distribution network will be approximately the clock distribution
delay times the peak-to-peak expected supply noise (assuming that
a 1% change in supply voltage leads to a 0.5% change in delay).
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Q: Should I make any special provisions when
incorporating a TCI PLL into my chip?
A: Yes. The chip should have separate analog supply pads for the PLL.
The PLL should be located near the edge of the chip, away from large
output busses. See the "User Guidelines" document for additional information.
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