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Will also Showcase other high-performance PLL, DLL and DDR PHY IP and its
powerful JSPICETM Design Environment
(JDETM)
June 23-25, 2025, Moscone Convention Center, West Hall, Booth #1637
Who
True Circuits, Inc. (TCI), a leading provider of analog and mixed-signal
intellectual property (IP) for the semiconductor, systems and electronics
industries.
What
At the 62nd Design Automation Conference (DAC), TCI will introduce an improved,
state-of-the-art digital LC PLL that includes an innovative digital control
algorithm that cuts the lock time by as much as 70% over previous versions, while
directly controlling the loop bandwidth accurately (by 0.1% of Fref or better) and
consistently across PVT variations through continuous background loop-gain
calibration. Called the Ultra+, this PLL is highly programmable so one PLL can be
used for all applications on a SoC. It has ultra-low jitter performance (<100fs)
for the most demanding SerDes and ADC reference clocks and ultra-wide
multiplication range (1-250,000) to support reference clocks from 32KHz to 1GHz.
The Ultra+ PLL also offers precise frequency control with a least 26 fractional
bits (at least 10 precise) for extremely high fractional-N resolution. It can also
generate precise and adjustable frequency spreading with programmable rate and
depth to meet tight FCC requirements. The Ultra+ PLL does all this while drawing
low power from a compact size. The PLL can be delivered as synthesizable or
hardened IP with a modular design, so customers can build their own features
easily and safely using hard macros and stock Verilog code.
TCI will also showcase its complete line of high performance and general
purpose analog and synthesizable PLL and DLL IP, as well as its innovative and
flexible DDR PHY IP. The high performance, silicon proven DDR PHY has fully
automatic training managed by a light weight special purpose processor, and
remarkable physical flexibility to adapt to each customer's die floorplan and
package. The PHY supports LPDDR5, DDR4, LPDDR4, DDR3, and LPDDR3 protocols, and
is available in a variety of TSMC processes from 40nm to 4nm. The availability of
this silicon proven PHY means customers can now license a PHY with significant
performance and features without all the implementation and timing closure
hassles that are common with current DDR offerings. During the show, we will be
giving short presentations and demos of our DDR PHY in action. This will be a
great opportunity to ask questions and learn what makes a TCI DDR PHY hard macro
one special piece of IP.
In addition to introducing JDE, TCI will also showcase its high performance,
silicon proven DDR PHY with fully automatic training managed by a light weight
special purpose processor, and remarkable physical flexibility to adapt to each
customer's die floorplan and package. The PHY supports LPDDR5, DDR4, LPDDR4,
DDR3, and LPDDR3 protocols, and is available in a variety of TSMC processes from
40nm to 3nm. The availability of this silicon proven PHY means customers can now
license a PHY with significant performance and features without all the
implementation and timing closure hassles that are common with current DDR
offerings. During the show, we will be giving short presentations and demos of
our DDR PHY in action. This will be a great opportunity to ask questions and
learn what makes a TCI DDR PHY hard macro one special piece of IP.
True Circuits will offer daily JSPICETM
Design Environment (JDETM) presentations and
demos highlighting the features and uses of this powerful design environment. JDE
has been under continuous development and use by True Circuits for over 27 years
to create complex analog and digital circuits from 250nm to 4nm. JDE greatly
simplifies and expedites the process of designing and characterizing circuits by
dramatically facilitating and enhancing the process of running simulations and
interpreting their results. A JDE ecosystem will allow open collaboration between
users, content creators and service providers that can help spur innovation and
dramatically reduce design time. We are glad to discuss how interested users,
whether individuals, students or employees of companies, can start benefitting
from and contributing to JDE!
As always, we are happy to discuss your chip requirements and timing needs,
and recommend the best analog or synthesizable PLL or DLL from our complete line
of high performance and general purpose timing IP. These high quality, low-jitter
PLL and DLL hard and soft macros are suited to a wide variety of interface
standards and chip applications. They are pin-programmable, highly process
tolerant, reusable and available for delivery in TSMC, GLOBALFOUNDRIES and UMC
processes from 180nm to 4nm.
When and Where
Moscone Convention Center, West Hall, San Francisco, CA
True Circuits Booth #1637
Monday - Wednesday, June 23-25, 10:00 AM to 6:00 PM
JDETM Presentation Schedule
Monday June 23, 11:00 AM, 1:00 PM and 3:00 PM
Tuesday June 24, 11:00 AM, 1:00 PM and 3:00 PM
Wednesday June 25 11:00 AM and 1:00 PM
Please register for a JDE presentation day and at
www.truecircuits.com/jspice_dac2023_pres.html.
If you would like a private JDE demo at DAC, please register at
www.truecircuits.com/jspice_dac_demo.html.
Contacts
For more information about True Circuits' PLLs, DLLs, DDR PHYs and
JDETM, please visit
www.truecircuits.com.
For more information about the Design Automation Conference, please visit
www.dac.com.
About JDETM
JDE is a powerful design environment developed and used by True Circuits over the
last 27 years to create complex analog and digital circuits from 250nm to 4nm. It
is a tightly integrated collection of tools and capabilities that greatly
simplifies and expedites the process of designing and characterizing circuits in
a standardized, centralized and repeatable way. JDE enables users to run
massively parallel simulations, either locally or in the cloud, or both with
unlimited JSPICETM simulator licenses. JDE
includes a measurement and data analysis environment that is packed with
functions and reduces massive data into insightful information that builds
intuition and encourages exploration. JDE incorporates text, processing code and
scripts that move analog design into the realm of modern software. JDE moves
layout from mostly hand-drawn to cell-based without losing the layout control
needed for critical circuits.
JDE provides users extended input preprocessing, directed logic synthesis,
Verilog A support, transient noise analysis, timing analysis, mixed-mode
simulation, generalized waveform analysis, parametric simulation sweeps and
optimization, parallel simulation job control, network process and cloud
management, and data reduction and output processing. Characterization flows
allow users to encapsulate all information needed to automatically and fully
characterize a design and even generate reports. High-speed analog and digital
designs can be deterministically placed and routed, allowing them to be process
independent. JDE also provides a powerful mechanism for schematic-based
electrical checks for use by users who want all of the advanced features of JDE
without understanding any of the details. While JDE includes the JSPICE simulator
with some features facilitated by the JSPICE language, it can work with any SPICE
simulator.
About the JDETM Ecosystem
JDE is intended to be an open design environment, easily accessible by a variety
of users, from universities and businesses to individual designers, all providing
content and services to make JDE the development environment of the future. The
JDE ecosystem will allow open collaboration between users, content creators and
service providers that can help spur innovation and dramatically reduce design
time. A strong ecosystem can populate libraries with rich content including
useful modules or complete designs, data analysis utilities, easily modified
characterization scripts, and test suites for common protocols or applications.
In addition to support and services from True Circuits, JDE users will also be
able to draw on ecosystem service providers with the staffing and expertise to
accelerate JDE adoption and ease-of-use. The future of semiconductors lies with
universities that attract and train engineering talent and JDE is positioned to
be their design environment of choice.
About the JDETM Membership Program
JDE is now available to users, whether individuals, students or employees of
companies, who submit a membership application at
http://www.truecircuits.com/jspice_beta.html. The application process will ask
users to agree to the terms of the JDE membership program, including providing
periodic feedback and participating in user forums. Users will be accepted by
True Circuits, at its sole discretion, into the program for a selected period of
time. Accepted users will be provided the JDE software suite, user guidelines,
related documentation and a True Circuits point of contact for user support and
feedback.
For more information about JDE, visit
www.truecircuits.com/jspice.html.
About True Circuits Analog PLLs and DLLs
True Circuits offers a complete family of standardized and silicon-proven general
purpose, clock generator, deskew, spread spectrum, IoT and Ultra PLLs, and
multi-slave and multi-phase DLLs that spans nearly all performance points and
features typically requested by ASIC, FPGA and SoC designers. These high quality,
low-jitter PLL and DLL hard macros are suited to a wide variety of interface
standards and chip applications. They are pin-programmable, highly process
tolerant and reusable. They are also easy to integrate and are fully supported,
so customers can reduce both design and silicon risks.
True Circuits PLLs support a wide range of frequencies, multiplication factors
and functions over which they deliver optimal performance, avoiding the cost and
complexity of licensing multiple point-solution PLLs or fiddling with digital
PLLs. TCI's PLLs are available with ring-oscillator and LC-tank architectures,
fractional-N division and frequency spreading for EMI reduction. TCI's DLLs are
available in multi-slave and multi-phase versions and different sizes and form
factors. They delay a set of signals by precise and adjustable fractions of a
reference clock cycle independent of voltage and temperature and are ideal for
high-speed DDR and ONFI interface applications. Customized PLL and DLL solutions
are also available for specialized chip applications.
True Circuits PLLs and DLLs are available for immediate customer delivery in
TSMC, GLOBALFOUNDRIES and UMC processes from 180nm to 3nm. For more information
about True Circuits IP products, visit www.truecircuits.com/tci_technology.html
and www.truecircuits.com/product_matrix.html.
About True Circuits Synthesizable PLLs and DLLs
The synthesizable Precision PLL generates multiple precision clocks supporting
any modulation scheme from almost DC to 10GHz. The outputs can be independently
dynamically programmed cycle-by-cycle to any clock period and the clock frequency
can be a precise ratio of floating point numbers times the reference frequency.
The integrated phase noise is better than 500fs RMS. It is ideal for SerDes,
processor and DVFS applications.
The synthesizable micro PLL is a small synthesizable general-purpose PLL that
multiplies the reference clock by any integer or fractional-N value from 1 to
500K. It supports reference clock frequencies as low as 32KHz and output
frequencies as high as 3GHz. It can stay locked to the reference clock while it
changes over a 10:1 frequency range. Because it is synthesizable, it can support
spreading as well as other modulation profiles. It is relatively low power, very
fast locking and can quickly restart from a sleep mode.
The synthesizable micro DLL is a small synthesizable DLL with a master and
multiple slaves topology. It can support reference frequencies typically in the
range of 500MHz to 3GHz and track reference changes over an 8:1 frequency range
while providing 9-bit accuracy in slave delay programming. Slave delays can be
changed glitch free and the DLL can quickly restart from a sleep mode. It has a
very small zero code offset that can be precisely cancelled.
About True Circuits DDR PHYs
The DDR PHY is a high-performance, scalable system using a radically new
architecture that continuously and automatically adjusts each pin individually,
correcting skew within byte lanes. This state-of-the-art tuning acts
independently on each pin, data phase and chip select value. Read gate and data
eye timing are also continuously adjusted. Fully automatic training is managed by
a light weight special purpose processor and includes multi-cycle write leveling
and read gate training and also read/write data eye training, including PHY Vref
and DRAM Vref settings.
The PHY employs a localized and optimized PHY-to-memory controller interface
to ease timing closure. The circuitry in each pin is able to measure the data eye
and jitter, and calculate flight delays. The PHY also includes a full speed
read/write BIST, which tests the complete read and write paths of every pin
simultaneously with pseudo-random data.
Remarkable physical flexibility allows the PHY to adapt to each customer's die
floorplan and package constraints, yet is verified and delivered as a unit for
easy timing closure with no assembly required. The PHY supports LPDDR5, DDR4,
LPDDR4, DDR3 and LPDDR3, and is DFI 5.1 compliant. When combined with an
appropriate DDR memory controller, a complete and fully-automatic DDR system is
realized.
The True Circuits DDR PHY is silicon proven and available for customer
delivery in a variety of TSMC processes from 40nm to 3nm. Interested customers
can obtain more product information on the web at
www.truecircuits.com/ddr_phy.html
or by contacting True Circuits at
sales@truecircuits.com.
About JDETM
JDE is a powerful design environment developed and used by True Circuits over the
last 27 years to create complex analog and digital circuits from 250nm to 4nm. It
is a tightly integrated collection of tools and capabilities that greatly
simplifies and expedites the process of designing and characterizing circuits in
a standardized, centralized and repeatable way. JDE enables users to run
massively parallel simulations, either locally or in the cloud, or both with
unlimited JSPICETM simulator licenses. JDE
includes a measurement and data analysis environment that is packed with
functions and reduces massive data into insightful information that builds
intuition and encourages exploration. JDE incorporates text, processing code and
scripts that move analog design into the realm of modern software. JDE moves
layout from mostly hand-drawn to cell-based without losing the layout control
needed for critical circuits.
For more information about JDE, visit
www.truecircuits.com/jspice.html.
About True Circuits
True Circuits develops and markets a broad range of industry leading PLLs, DLLs
and DDR PHY hard macros for ICs for the semiconductor, systems and electronics
industries. TCI's robust state-of-the-art circuits, methodical and proven design
strategy, and close association with the world's leading foundries, IDMs, and
design services companies allow the company to quickly and reliably create new
and innovative designs in a variety of advanced process technologies. Over the
last 27 years, True Circuits has distinguished itself as the technology leader in
the timing IP space, and its PLLs and DLLs are used extensively around the world
in its customers' products with production volumes well into the billions.
True Circuits is headquartered at 4300 El Camino Real, Suite 200, Los Altos,
California 94022 and can be found on the web at www.truecircuits.com. Product
inquiries can be made by calling the company directly at (650) 949-3400 or via
e-mail at sales@truecircuits.com.
Press Contact: Kimberly Toan, True Circuits, Inc., (650) 949-3400, Ext. 3404,
kim@truecircuits.com.
Acronyms and definitions
ASIC Application Specific IC
DLL Delay-Locked Loop
DDR Double Data Rate
FPGA Field Programmable Gate Array
IC Integrated Circuit
IoT Internet of Things
IP Intellectual Property
ONFI Open NAND Flash Interface
PLL Phase-Locked Loop
SoC System on a Chip
The "Ultra+ PLL" is a trademark of True Circuits, Inc.
The "JDE" logo is a trademark of True Circuits, Inc.
"JSPICE" is a trademark of True Circuits, Inc.
"Precision PLL" is a trademark of True Circuits, Inc.
"micro PLL" is a trademark of True Circuits, Inc.
"micro DLL" is a trademark of True Circuits, Inc.
"IoT PLL" is a trademark of True Circuits, Inc.
The True Circuits logo is a trademark of True Circuits, Inc.
All other trademarks and tradenames are the property of their respective owners.
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