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"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading
design portfolio and flow, our ASIC customers benefit with exceptional
performance and reliability. Combined with our custom chip
design expertise, these hard macros enable us to quickly and
cost-effectively implement ASIC designs with analog components for
high-volume applications."
Prasad Subramaniam Vice President Design Technology eSilicon
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When calculating the timing budgets, one may need to consider the
worst-case static phase offset, duty cycle error, cycle-to-cycle
jitter, and possibly tracking jitter from the PLL, the worst-case skew
and jitter from the clock distribution, and the worst-case setup,
hold, and clock-to-output times for the clocked elements.
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