The quality of a generated clock is measured by how much you have to degrade your timing budgets to account for imperfections in the PLL. The PLL's maximum output jitter directly subtracts from the time available to your combinational logic to make your speed paths. A lower output jitter figure can get you that much closer to making your timing goals. TCI PLLs are designed from the outset with the goal of low jitter in a noisy mixed-signal environment.

Moreover, the performance of the PLL that you buy directly impacts the AC timing specifications that you promise your customers. Both output jitter and skew can subtract from the timing margin between your chip and the rest of the system. A poor PLL can make it difficult for a customer to use your chip, which can increase their time to market, reduce their packaging flexibility, or lead to poor reliability in service. In the worst case a poor PLL can convert a design win into a loss. The exceptional performance offered by TCI PLLs makes it easy for your customers to use your chip and can enhance your reputation as a supplier.