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"True Circuits provided us with multi-phase clock generator PLLs that
met all our performance requirements and are now enabling our
customers to meet their own price and performance goals in the
wireless infrastructure and peripheral equipment markets."
Darrell Burns, Vice President of Engineering, Ubicom
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The cycle-to-cycle jitter for a divided output clock is the same
percentage of the divided clock period as that for an undivided
clock in the worst case of low-frequency supply/substrate noise.
However, the cycle-to-cycle jitter for any divided clock expressed
in units of time cannot exceed twice the long-term jitter by their
definitions.
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