"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies

When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.