"We have been licensing TCI PLLs for our network processors and data and traffic management chips for two years. TCI has always delivered PLLs to us that worked the first time. They have spec'ed and delivered the PLLs as promised, and their expertise in PLL design has been unquestionable."

George Serhan, VLSI Director, AMCC

The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.