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"The increasing demand for performance-intensive handheld devices and rising
time-to-market pressures heightens the need for design turnkey providers to
endow ASIC customers with more predictable and robust SoC solutions. With
True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter
for DDR 800Mbps and enter into mass production with very stable yield."
Yao Lee Strategic Marketing Manager Alchip Technologies
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The cycle-to-cycle jitter for a divided output clock is the same
percentage of the divided clock period as that for an undivided
clock in the worst case of low-frequency supply/substrate noise.
However, the cycle-to-cycle jitter for any divided clock expressed
in units of time cannot exceed twice the long-term jitter by their
definitions.
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