The IoT PLL is designed for very low power, sipping only about 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication factors up to 8192, allowing the PLL to run off of a small and inexpensive 32KHz crystal and still clock a 32-bit CPU at up to around 250MHz. It is ideal for IoT applications like wearables and senor devices, where the power-performance profile must be managed tightly, and possibly over a very wide frequency range.

Version: 1.5


Divided reference frequency range

30KHz – 138MHz

Total output frequency range

1.88MHz – 275MHz

/1 output frequency range

30MHz – 275MHz

Reference divider values


Feedback divider values

2–8192 (even only)

Output divider values

1, 2–16 (even only)

/1 output multiples of div. reference


Feedback signal delay (max)

n/a (FB internal)

Output duty cycle (nom, tol)

50%, +/–5% (/1), +/–2% (/N)

Static phase error (max)


Period jitter (P-P) (max)

Input-to-output jitter (P-P) (max)

Power dissipation (nom)

Reset pulse width (min)


Reset /1 output frequency range

15MHz – 138MHz

Lock time (min allowed)

/1 freq. overshoot (full-~/half-~) (max)

Area (including isolation) (max)

Number of PLL supply pkg. pins

1 VDDA, 1 VSSA (preferred)

Low freq. supply noise est. (P-P) (max)

10% VDDA

Low freq. sub. noise est. (P-P) (max)

10% VDDA

Ref. input jitter (long-term, P-P) (max)

Reference H/L pulse width (min)

Process technology

TSMC CL013LP 130nm

Supply voltage (VDD, VDDA) (nom, tol)

1.5V, +/–10%

Junction temperature (nom, min, max)

70C, –40C, 125C

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