"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas

Not usually. All our cell names are prefixed by "TCI_cellname_". As a result, our PLLs do not conflict with each other, and they usually don't conflict with our customers' cell names.