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"We chose TCI because of their expertise in PLLs and the proven
nature of their PLL designs. By going with TCI in the future, we feel
we can spend more time designing our embedded cores and less time doing
test chip integration work."
Ken Reimer, Austin Design Center Manager, ARM
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The Verilog model is very close but not perfect.
- In steady state, the Verilog model does not model any jitter that
might be present in the real PLL.
- During startup, the Verilog model will achieve lock much more quickly than the actual PLL....
- ...
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