"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



The Verilog model is very close but not perfect.

  • In steady state, the Verilog model does not model any jitter that might be present in the real PLL.
  • During startup, the Verilog model will achieve lock much more quickly than the actual PLL....
  • ...


30 May 16 True Circuits Attends Design Automation Conference

14 Mar 16 True Circuits Announces New Line of IoT PLLs

05 Jun 15 True Circuits Attends Design Automation Conference

06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

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