"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology

When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.

05 Jun 15 True Circuits Attends Design Automation Conference

06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

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