"Our network processors offer highly integrated voice and data capabilities by combining powerful digital signal processors, flexible packet-processing engines, and industry-standard streaming interfaces all on a single die. True Circuits has enabled these products to shine with highly differentiated PLL and DLL IP over three process generations (90nm, 65nm and 40nm). We can count on True Circuits to deliver first time working silicon and faster time to market."

Surinder Dhaliwal
Executive Director
VLSI Core Engineering
Mindspeed Technologies

The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.