"Our mission is to provide predictable, reliable and cost-effective ASIC solutions, while reducing risk at each step of the process and improving time-to-market. True Circuits PLLs and DLLs are feature rich, easily integrated and well supported, helping us to deliver quality analog IP and faster design implementations to our ASIC customers."

Hans Bouwmeester
Director of IP
Open-Silicon



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


7 Apr 15 TSMC NA Technology Symposium
San Jose, California

16 Apr 15 TSMC NA Technology Symposium
Austin, Texas

6-8 Jun 15 Design Automation Conference
San Francisco, California

17 Sep 15 TSMC OIP Ecosystem Forum
San Jose, California

Copyright © 2002-2015 True Circuits, Inc. All Rights Reserved