"With True Circuits' silicon-proven PLLs and DLLs in our industry-leading design portfolio and flow, our ASIC customers benefit with exceptional performance and reliability. Combined with our custom chip design expertise, these hard macros enable us to quickly and cost-effectively implement ASIC designs with analog components for high-volume applications."

Prasad Subramaniam
Vice President Design Technology
eSilicon



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


1 May 18 TSMC NA Technology Symposium
Santa Clara, California

9 May 18 TSMC NA Technology Symposium
Austin, Texas

22 May 18 TSMC China Technology Symposium
Shanghai, China

25-27 Jun 18 Design Automation Conference
San Francisco, California

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