"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



Given that we maintain state-of-the-art PLL intellectual property, we cannot perform such consulting without risking contamination which will compromise our business model.


7 Apr 15 TSMC NA Technology Symposium
San Jose, California

16 Apr 15 TSMC NA Technology Symposium
Austin, Texas

8-10 Jun 15 Design Automation Conference
San Francisco, California

17 Sep 15 TSMC OIP Ecosystem Forum
San Jose, California

Copyright © 2002-2015 True Circuits, Inc. All Rights Reserved