"We have been licensing TCI PLLs for our network processors and data and traffic management chips for two years. TCI has always delivered PLLs to us that worked the first time. They have spec'ed and delivered the PLLs as promised, and their expertise in PLL design has been unquestionable."

George Serhan, VLSI Director, AMCC

When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.