"We selected a PLL from TCI because of the company's PLL expertise and reputation for supplying proven PLL hard macros. The TCI 1.2GHz clock generator PLL is the core component that allows the multi-rate SONET/SDH ports on the ADM-on-a-Chip to operate within the required industry jitter specifications across all supported rates."

Kent Goodin
Vice President
VLSI Engineering
Parama Networks

A TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. Spread-spectrum PLLs can also be used to generate the system clock to lower EMI emissions.

7 Apr 15 TSMC NA Technology Symposium
San Jose, California

16 Apr 15 TSMC NA Technology Symposium
Austin, Texas

8-10 Jun 15 Design Automation Conference
San Francisco, California

17 Sep 15 TSMC OIP Ecosystem Forum
San Jose, California

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