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"We selected a PLL from TCI because of the company's PLL expertise and
reputation for supplying proven PLL hard macros. The TCI 1.2GHz clock
generator PLL is the core component that allows the multi-rate SONET/SDH
ports on the ADM-on-a-Chip to operate within the required industry
jitter specifications across all supported rates."
Kent Goodin, Vice President, VLSI Engineering, Parama Networks
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When calculating the timing budgets, one may need to consider the
worst-case static phase offset, duty cycle error, cycle-to-cycle
jitter, and possibly tracking jitter from the PLL, the worst-case skew
and jitter from the clock distribution, and the worst-case setup,
hold, and clock-to-output times for the clocked elements.
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