"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


22 Apr 14 TSMC NA Technology Symposium
San Jose, California

1 May 14 TSMC NA Technology Symposium
Austin, Texas

2-4 Jun 14 Design Automation Conference
San Francisco, California

30 Sep 14 TSMC OIP Ecosystem Forum
San Jose, California

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