"True Circuits provided us with multi-phase clock generator PLLs that met all our performance requirements and are now enabling our customers to meet their own price and performance goals in the wireless infrastructure and peripheral equipment markets."

Darrell Burns
Vice President of Engineering
Ubicom

When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.