"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



Given that we maintain state-of-the-art PLL intellectual property, we cannot perform such consulting without risking contamination which will compromise our business model.


15 Mar 17 TSMC NA Technology Symposium
San Jose, California

22 Mar 17 TSMC NA Technology Symposium
Austin, Texas

19-21 Jun 17 Design Automation Conference
Austin, Texas

13 Sep 17 TSMC OIP Ecosystem Forum
San Jose, California

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