"We selected TCI's clock generator PLL because of its small size, wide frequency range and superior low-jitter performance. This will enable our ASIC customers to successfully implement multiple SPI-4.2 macros in their high-end telecommunication ASICs and help meet the tight jitter and power budgets required for 10 Gbps SONET/SDH systems."

Hideya Horikawa
Senior Design Engineering Manager
Renesas



A TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. Spread-spectrum PLLs can also be used to generate the system clock to lower EMI emissions.


15 Mar 16 TSMC NA Technology Symposium
San Jose, California

24 Mar 16 TSMC NA Technology Symposium
Austin, Texas

6-8 Jun 16 Design Automation Conference
Austin, Texas

22 Sep 16 TSMC OIP Ecosystem Forum
San Jose, California

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