"Nuvoton Israel needed a high performance, wide spectrum, scalable and accurate timing solution for our industry leading server management SoC design. We found True Circuits' clock generator PLLs a perfect match to our design needs in various process nodes to date."

Uri Trichter
Senior Director Server BU
Nuvoton Technology Corp.



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


22 Apr 14 TSMC NA Technology Symposium
San Jose, California

1 May 14 TSMC NA Technology Symposium
Austin, Texas

2-4 Jun 14 Design Automation Conference
San Francisco, California

30 Sep 14 TSMC OIP Ecosystem Forum
San Jose, California

Copyright © 2002-2014 True Circuits, Inc. All Rights Reserved