"The Livanto™ wireless-soft modem is targeted at next generation mobile phones and high performance wireless applications, plus it is fabricated in a 90nm process, so we spent a fair amount of time selecting suitable IP and designing the best clocking system possible. True Circuits' IP gave us high implementation flexibility and provided us with the functionality we required, while meeting our strict power, area and cost targets."

Peter Hughes, Vice President of Silicon Operations, Icera Inc.



When calculating the timing budgets, one may need to consider the worst-case static phase offset, duty cycle error, cycle-to-cycle jitter, and possibly tracking jitter from the PLL, the worst-case skew and jitter from the clock distribution, and the worst-case setup, hold, and clock-to-output times for the clocked elements.


21 Jul 09 True Circuits Attends Design Automation Conference

06 Apr 09 True Circuits 40nm PLL and DLL Hard Macros Featured at TSMC Technology Symposium in San Jose

15 Jan 09 See Our Product Showcase in the Jan-Feb Issue of Chip Design

22 Sep 08 True Circuits Analog PLL & DLL Hard Macros Featured at GSA Suppliers Expo

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