"True Circuits provided us with multi-phase clock generator PLLs that met all our performance requirements and are now enabling our customers to meet their own price and performance goals in the wireless infrastructure and peripheral equipment markets."

Darrell Burns
Vice President of Engineering
Ubicom



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

03 Jun 13 True Circuits Introduces Revolutionary New DDR 4/3 PHY at Design Automation Conference

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