"The increasing demand for performance-intensive handheld devices and rising time-to-market pressures heightens the need for design turnkey providers to endow ASIC customers with more predictable and robust SoC solutions. With True Circuits' PLL and DLL at TSMC 55nm, we were able to achieve low jitter for DDR 800Mbps and enter into mass production with very stable yield."

Yao Lee
Strategic Marketing Manager
Alchip Technologies



A TCI deskew PLL, which provides phase-aligned divide by 1, 2, and 4 clock outputs, can facilitate generating the system clock signals, data strobes, and internal double frequency clocks used to clock the output data. Spread-spectrum PLLs can also be used to generate the system clock to lower EMI emissions.


05 Jun 15 True Circuits Attends Design Automation Conference

06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

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