"Our network processors offer highly integrated voice and data capabilities by combining powerful digital signal processors, flexible packet-processing engines, and industry-standard streaming interfaces all on a single die. True Circuits has enabled these products to shine with highly differentiated PLL and DLL IP over three process generations (90nm, 65nm and 40nm). We can count on True Circuits to deliver first time working silicon and faster time to market."

Surinder Dhaliwal
Executive Director
VLSI Core Engineering
Mindspeed Technologies

The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.

7 Apr 15 TSMC NA Technology Symposium
San Jose, California

16 Apr 15 TSMC NA Technology Symposium
Austin, Texas

8-10 Jun 15 Design Automation Conference
San Francisco, California

17 Sep 15 TSMC OIP Ecosystem Forum
San Jose, California

Copyright © 2002-2015 True Circuits, Inc. All Rights Reserved