"We selected True Circuits because of their deep expertise and proven ability in high-performance timing circuits. Using their programmable IP, our team was able to implement multiple PLL and DLL blocks under an aggressive schedule to provide our customers with complete timing flexibility for even the most demanding system applications."

Stefan Tamme
Vice President of Sales and Marketing
Leopard Logic



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


05 Jun 15 True Circuits Attends Design Automation Conference

06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

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