"Our connected media devices deliver class-leading performance at the lowest possible power consumption. True Circuits' clock generator PLLs have wide programmable frequency ranges, low jitter, small area and low power. This mix of performance and functionality enables us to offer our customers highly differentiated IP cores in advanced process technologies."

Mark Dunn
General Manager IMGworks
Imagination Technologies



The cycle-to-cycle jitter for a divided output clock is the same percentage of the divided clock period as that for an undivided clock in the worst case of low-frequency supply/substrate noise. However, the cycle-to-cycle jitter for any divided clock expressed in units of time cannot exceed twice the long-term jitter by their definitions.


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