"Our connected media devices deliver class-leading performance at the lowest possible power consumption. True Circuits' clock generator PLLs have wide programmable frequency ranges, low jitter, small area and low power. This mix of performance and functionality enables us to offer our customers highly differentiated IP cores in advanced process technologies."

Mark Dunn
General Manager IMGworks
Imagination Technologies



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


05 Jun 15 True Circuits Attends Design Automation Conference

06 Apr 15 True Circuits Announces New Line of PLLs, The Ultra PLL

30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

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