"We selected True Circuits because of their deep expertise and proven ability in high-performance timing circuits. Using their programmable IP, our team was able to implement multiple PLL and DLL blocks under an aggressive schedule to provide our customers with complete timing flexibility for even the most demanding system applications."

Stefan Tamme
Vice President of Sales and Marketing
Leopard Logic



The chip should have separate analog supply pads for the PLL. The PLL should be located near the edge of the chip, away from large output busses. See the "User Guidelines" document for additional information.


30 May 14 True Circuits Showcases Revolutionary New DDR 4/3 PHY at Design Automation Conference

22 Oct 13 See Our Ad in the Fall Issue of Chip Design Magazine

03 Jun 13 True Circuits Introduces Revolutionary New DDR 4/3 PHY at Design Automation Conference

28 Jan 13 See Our Ad in the Winter Issue of Chip Design Magazine

Copyright © 2002-2014 True Circuits, Inc. All Rights Reserved