"TCI's low-jitter high-resolution clock generator PLL helped us produce a more flexible IC for our customers and enabled us to meet our time-to-market goals. The True Circuits IP enabled us to set up multiple clock domains on a single SOC that previously required five separate ICs."

Gerard Yeh
Director of VLSI Design
Oak's TeraLogic Group



We provide all of the following for each of our PLLs:

  • Complete specifications
  • User guidelines
  • Behavioral simulation model
  • Complete layout (GDSII)
  • Layout vs. schematic netlist
  • ...


5 Mar 13 Common Platform Technology Forum
Santa Clara, California

9 Apr 13 TSMC NA Technology Symposium
San Jose, California

16 Apr 13 TSMC NA Technology Symposium
Austin, Texas

18 Apr 13 GSA Silicon Summit
Mountain View, California

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